My Education

  • 2013 - 2015
    Microsystems Engineering - Master of Science (M.Sc.)    image
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    September 2013 - June 2015

    EECS - Department of Electrical Engineering and Computer Science

    Masdar Institute (In collaboration with MIT)
    Masdar City, AbuDhabi, UAE.

    Thesis Title: An Integrated, Low-Power Platform for Continuous Congestive HeartFailure Monitoring using Body-Channel Communication.
    Advisor: Prof. Ibrahim (Abe) M. Elfadel, Senior Member, IEEE and Head of Institute Center for Microsystems (iMicro).
    Co-Advisors: Assoc. Prof. Jerald Yoo, Senior Member, IEEE and Asst. Prof. Ayman Shabra, Member, IEEE.
    Accolade: Institute's Best Thesis Award (2015) and Microsystems Department's Best Thesis Award (2015).
    Sponsors and Collaborators: SRC, ATIC, MIT, Texas Instruments, Global Foundries.
    Knowledge Involved: IC / VLSI Design, FPGA Based Design, Algorithm Development, System Architecture & Integration, PCB Design, Communication & Synchronization, Power Management, Testing and Analysis.

    Thesis Details : Please see Research & Projects section.

    Major Subjects:

    • Analysis and Design of Digital Integrated Circuits
    • Analysis and Design of Analog Integrated Circuits
    • Digital Systems Laboratory
    • High-Speed Communication Circuits
    • Integrated Microelectronic Devices
    • Micro/Nano Processing Technology
    • Advanced Signal Processing
    • Sustainable Energy
    • Academic Writing for Research
  • 2004 - 2008
    Electrical Engineering – Bachelor Of Science (B.Sc.)    image
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    August 2004 - June 2008

    EE - Department of Electrical Engineering

    National University of Computer and Emerging Sciences (FAST-NUCES)
    Lahore, Pakistan.

    Project Title: Learning Robo - An external and general learning systems for machines.
    Advisor: Asst. Prof. Imtiaz Tariq.
    Accolade: Outstanding Project Award in EE department sponsored in-house competition.
    Knowledge Involved: FPGA Based Design, Microcontrollers, Algorithm Development, System Architecture & Integration, PCB Design, Communication, Testing and Analysis.

    Major Subjects:

    • Electric Circuit Analysis
    • Electronics
    • Digital Logic Design
    • Computer Architecture
    • Microprocessor Interfacing & Programming
    • Operating System
    • Electromagnetic Theory
    • Signals & Systems
    • Digital Signal Processing
    • Digital Image processing
    • Digital Communication
    • C++ programming
    • Object Oriented Programming
    • Data Structures
    • Calculus
    • Multi Variable Calculus & Complex Analysis
    • Linear Algebra & Differential Equations
    • Feedback Control System
    • Telecommunication Systems
    • Wireless & Mobile Communication
    • Satellite Communication
    • Wave Propagation & Antenna Theory
    • Final Year Project
  • 2002 - 2004
    Higher Secondary School Certificate-Intermediate Exam (F.Sc.)    image
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    June 2002 - June 2004

    Pre-Engineering

    The Forman Christian College (A Chartered University)
    Lahore, Pakistan.

    Major Subjects:

    • Physics
    • Chemistry
    • Mathematics
  • 2000 - 2002
    Secondary School Certificate-Matriculation    image
    June 2000 - June 2002

    Faculty of Science

    GOVT. Pilot Secondary School (Excellent Section)
    Lahore, Pakistan.

    Major Subjects:

    • Physics
    • Chemistry
    • Mathematics
    • Biology

My Experience

Research Experience:

Please see "Research & Projects" section.

Professional Experience:

  • 2011 - 2013
    Senior Development Engineer - Mentor Graphics    image
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    Feb. 2011 - Aug. 2013

    Mentor Graphics

    Lahore, Pakistan.

    Primary work was related to Digital and Embedded Systems:
    • Employing a variety of devices and development boards from vendors such as Xilinx, Texas Instruments, Freescale, Logic PD, Beagle, and ARM.
    • And, using different design tools and techniques such as Verilog/VHDL, embedded programming, board support packages, RTOS (Xilkernel and Mentor Nucleus) and, third-party IPs integration.

    Accolade: Outstanding Performance Award
  • 2008 - 2009
    Embedded System Engineer - Powersoft19    image
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    Sep. 2008 - Sep. 2009

    Powersoft19

    Lahore, Pakistan.

    Primary work was related to Embedded Systems:
    • Involved in an outsourced project of USA based Company, ISC, to develop devices to detect various types of harmful gasses for the workers during their work in the mines..
    • Involved in another outsourced project, ECLO-II from Germany, to automate the high speed trains in EUROPE.
  • -
    Freelance Work    image
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    • Factory machines' tracking system for an ISO certified socks knitting company (used microcontrollers as processing devices).
    • Wholesale business management system software.
    • Couple of websites.

Awards & Honors

  • 2015
    Institute's Best M.Sc. Thesis Award    image
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    An Integrated, Low-Power Platform for Continuous Congestive Heart-Failure Monitoring using Body-Channel Communication.
    Masdar Institute.

    Details : Please see Research & Projects Section.
  • 2015
    Department's Best M.Sc. Thesis Award    image
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    An Integrated, Low-Power Platform for Continuous Congestive Heart-Failure Monitoring using Body-Channel Communication.
    Masdar Institute.

    Details : Please see Research & Projects Section.
  • 2012
    Outstanding Performance Award    image
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    Mentor Graphics.

  • 2004
    Outstanding Project Award    image
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    Learning Robo - An external and general learning systems for machines.
    EE department sponsored in-house competition, FAST-NUCES.

  • -
    All Other Awards    image
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    1 - Winner of International Programming Competition (ACM mentored) in SOFTEC at FAST-NUCES, Lahore.
    2 - Multiple time winner of Speed Programming Competition in NASTEC at NUST, Islamabad.
    3 - Stood in top 5 teams in International Engineering Project Competition in SOFTEC at FAST-NUCES, Lahore.
    4 - Invited several times to judge different engineering competitions in ACM and SOFTEC events at FASTNUCES, Lahore.
    5 - Secured several scholarships and financial aids to support my education.

Extracurricular & Hobbies

  • Table Tennis & other indoor spots
  • Cricket
  • Reading
  • Graphic designing and animations
  • Sound and Video editing

Research Experience

  • 2013 - Now
    Research Assistant - Institute Center for Microsystems (iMicro)    image
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    Sep. 2013 - Present

    Institute Center for Microsystems (iMicro)

    ATIC-SRC Center of Excellence for Energy Efficient Electronics Systems (ACE4S)

    Masdar Institute of Science and Technology (In collaboration with MIT)
    Abu-Dhabi, UAE.

    Task Leader: Prof. Ibrahim (Abe) M. Elfadel (MI), Head of Institute Center for Microsystems (iMicro).
    Co-Task Leaders:
    • Prof. Anantha P. Chandrakasan (MIT).
    • Assoc. Prof. Jerald Yoo (MI).
    • Asst. Prof. Ayman Shabra (MI).


    • Invented a low-power and high data rate single-wire communication technique, PulsedIndex Communication (PIC).
      • IP implementation in Verilog for FPGA (Virtex-7), ASIC flow (synthesized with 65nm CMOS technology), and in embedded C using TI MSP430.
      • Transceivers implementation in 65nm CMOS technologies.
      • Optimization and Analysis.
      • Power management using pulse width controller (45nm CMOS technology).
    • Adaptive Pulsed-Index Communication (A-PIC) – Currently in progress.
      • Auto negotiation of PIC parameters such as speed, delays etc. between the connected devices via Single-Eire, thus eliminating the need for compile time settings.
      • On-the-fly detection and enumeration of new devices connected to the single-wire.
      • Automatic device ID assignment – no need to assign slave device IDs in advance.
      • Verilog HDL implementation and testing using master-slave network topology.
    • Walk Cycle Demonstrator Version A (CHF Monitoring System – Thesis implementation).
      • Worked as a system architect, thereby actively participated in project planning.
      • Proposed a novel architecture of monitoring system using shoe mounted sensor nodes, human body as communication medium, and VLSI implemented personal assistant.
      • Defined standard system interfaces to integrate all modules that are in simultaneous development.
      • Implemented and tested a full demo using sensor node and body channel models over Virtex-7 development board.
    • CHF Monitoring System Demonstrator Version B (Extension of Demo A).
      • Wearable system – Each end (left foot, right foot, and personal assistant) works as an independent device.
      • Implemented and tested realistic body channel communication transceivers to send and receive signals through human body using Pulsed-Index Communication (PIC).
      • Embedded Systems-based implementation and testing of a full demo B using TI MSP432 microcontrollers.
      • Personal assistant implementation using Windows 10 IoT core based application and using Raspberry Pi.
      • Modular and flexible, so that it can integrate a rage of sensor insole platforms, and can use existing human walk-cycle databases to analyze and test a variety of estimation algorithms.
    • Continuous Real-time Monitoring and early Detection of Congestive Heart-Failure Conditions: An Enhanced Low-Power Adaptive-Grid Run-Time Systematic Sampling Technique.
      • Proposed a new data sampling technique to reduce greatly the number of weight samples required to acquire and analyze.
      • The technique tends to reduce the device power consumption due to the less requirement on storage memory, processing, and communication.
      • It predicts CHF through the detection of weight change patterns in advance to the patient’s hospitalization by almost 5 days.
    • Body Channel Communication demonstrator using music signal transmission through human skin.
    • IoT characterization and testing platform using a network of devices connected via PIC single wire protocol. Implemented on Virtex-7 using PIC and TI MSP430 Verilog IP.
    • ALU Architecture implementation using 45nm CMOS technology.
    • Differential Digital Clock & Data recovery (CDR) using Virtex-7 FPGA.
    • Multiparameter Heart Failure Monitoring Algorithm-Initial Implementation using 45nm CMOS technology.
  • 2009 - 2011
    Design Engineer (Team Lead) - Center for Excellence in FPGA/ASIC Research (CEFAR)    image
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    Oct. 2009 - Jan. 2011

    Center for Excellence in FPGA/ASIC Research (CEFAR)

    National University of Sciences and Technology (NUST)
    Islamabad, Pakistan.

    Worked on several projects such as:
    • Secure dial project to securely transmit the speech over telephones using Xilinx Virtex-5 FPGA.
    • AES encryption and Decryption implementation on Xilinx Virtex-5 FPGA.
    • ADPCM implementation on Xilinx Virtex-5 FPGA.
    • High speed DVB-Common Scrambling Algorithm (CSA) implementation on Xilinx Virtex-5 FPGA.
    • High speed SHA-1 Security Algorithm implementation on Xilinx Virtex-4 FPGA.
    • Power optimization techniques at RTL level to reduce power consumption of FPGA based system designs.
  • 2008 - 2015
    University research projects mentoring and supervision    image
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    Aug. 2008 - June 2015
    • Electrical Engineering Department, National University of Computer and Emerging Sciences (FAST-NUCES), Lahore.
      • FPGA based CPPI Supported Mini-Computer. Hardware (XilAnt) on Virtex-4 FPGA and OS Wrapper (XilAntOS) using Xikernel/Mentor-Nucleus and embedded C.
        • 2nd Position in SOFTEC all Pakistan Engineering Project Competition (2013).
      • Improved FALCON-A Processor Architecture over FPGA (Virtex-4).
      • FM Antenna Direction & Angle Detector using FPGA Platform (Virtex-4).
      • FPGA Based Signal Generator & Shifter (Spartan-3E).
      • FPGA Implemented Face Recognition System (Virtex-4).
      • High Speed Big Data (0-512bit) Multiplier over FPGA (Spartan-3).
      • Energy Management System (Virtex-4).
    • Computer Engineering Department, COMSATS Institute of Information Technology, Lahore.
      • Custom OS image editor using FPGA based embedded system (Spartan-6).
      • Best Project Award (2015).

M.Sc. Thesis

Thesis Title:

An Integrated, Low-Power Platform for Continuous Congestive HeartFailure Monitoring using Body-Channel Communication.

Advisor:

Prof. Ibrahim (Abe) M. Elfadel, Senior Member, IEEE and Head of Institute Center for Microsystems (iMicro).

Co-Advisors:

Assoc. Prof. Jerald Yoo, Senior Member, IEEE and Asst. Prof. Ayman Shabra, Member, IEEE.

Sponsors and Collaborators:

SRC, ATIC, MIT, Texas Instruments, Global Foundries.

Knowledge Involved:

IC / VLSI Design, FPGA Based Design, Algorithm Development, System Architecture & Integration, PCB Design, Communication & Synchronization, Power Management, Testing and Analysis.
image Institute's Best Thesis Award (2015) and Microsystems Department's Best Thesis Award (2015).
image Read my Thesis Here.
image View my Thesis defence presentation Here.

Abstract:

This research presents a novel ultra-low power wearable system for Congestive Heart Failure (CHF) monitoring using the continuous measurement of a patient's weight to detect changes in body mass and fluid composition. Shoe-integrated sensor arrays are used to continuously measure the weight, and an electronic digital assistant, implemented in VLSI, is used to further analyze the acquired measurements in real time. To achieve ultra low-power operation, the human body is used as a communication medium between the shoe-mounted sensors and the digital assistant. The single-channel behavior of the human body is accommodated with a novel, simple yet robust single-wire signaling technique that we have called Pulsed-Index Communication (MI provisional patent pending). This signaling technique significantly reduces the system footprint and its overall power consumption as it entirely eliminates the need for circuitry dedicated to clock and data recovery. The CHF system has been fully prototyped using a cutting-edge FPGA platform, namely, Virtex 7 from Xilinx. The prototype, which integrates models for footwear, body area network (BAN), and back-end digital electronics, has been rigorously and successfully tested. This highly modular system is being used to implement, analyze and compare various pattern recognition algorithms for the early detection of congestive heart failure. The research described in this thesis has been conducted under the Abu Dhabi - SRC Center of Excellence on Energy-Efficient Electronic Systems (ACE4S).

System Diagram:

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Publications & Patents:

Please see "Publications & Patents" section.

Research & Projects Afore

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    FPGA based CPPI Supported Mini-Computer    image

    This was to design a computer system (in the sense of Embedded system) that have normal hardware user interfaces like mouse, keyboard, LCD/Monitor etc. and have some graphical OS like interface to interact with the computer in order use functionalities supported with this Mini-Computer. At software level proper OS driver layer was developed to give a higher level APIs to use in the supported applications like calculator, notepad, serial terminal etc. Xilkernel was used as kernel over MicroBlaze customized processor while the Xilinx Virtex-4 FPGA based ML403 board was used as hardware platform.

    XilAnt is a Mini-Computer System developed by customizing & implementing Microblaze Processor based Hardware Platform, newly 100% self-developed Graphical OS management module over Xilkernel (RTOS) and with few basic applications running over this OS in order to demonstrate the related capabilities using 100 MHz of clock only.

    XilAntOS is a lightweight, customizable, and portable small graphical OS for XilAnt Mini-Computer. New application can be added quickly and easily within few minutes to such a system leaving rest of the management over XilAntOS. It can also be easily used with other various RTOS and different processor based platforms with the porting of OS driver layer only.

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    Learning Robo - An external and general learning systems for machines    image

    In this project an external and general learning systems based on the latest technologies like FPGA (Xilinx Spartan-3) is developed, implemented and success fully tested (without any interference with the internal circuitry of the Robot) using VHDL. This system interprets and learns the human commands to a ROBOT with which it is interfaced.

    The circuit for this purpose must have sufficient and efficient memory system, in order to be the brain of the Robot. This project can be used by all types of users like home, office, and factories, etc.. Especially this can be very useful for disabled people. For example a Robot with this type of circuitry can fetch a glass of water, tea or may guide a blind person to his room, etc.

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    Energy Management System    image

    Implementation of such system that can manage the energy system of some place like home/office efficiently. It was capable of switching the appliances to different energy sources on the basis of bearable load to a particular energy source. It was also working on the basis of appliances priorities either the default ones or user provided. This project was implemented using Xilinx Virtex-4 FPGA.

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    FALCON-A Processor Architecture over FPGA    image

    FALCON-A processor based simulation was developed as PC based application for the students in order to teach them about the basics of processor architecture and its processing. Idea was to develop it with improvements on FPGA to teach students not only the processing while running it on a real time hardware but also to teach them that how the architecture is developed using hardware elements. This research & development was carried out over Xilinx Virtex-4 FPGA.

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    High Speed Big Data (0-512bit) Multiplier over FPGA    image

    This little research work was to develop efficient 512x512 bit multiplier in order to use in a high speed algorithm. It was developed to use minimum resources of FPGA but still fast enough to support such a big multiplication in the required time. This was developed using Xilinx SystemGenerator.

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    Secure Dial    image

    Secure dial project to securely transmit the speech over telephones using Xilinx Virtex-5 FPGA.

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    Machines Tracking System    image

    A project that is to make a cheap and reliable system that tracks a number of machines and then stores information on a single computer via serial port communication. A device is developed that tracks the machines and sends info of all machines using a single wire using a serial port communication without data interference and lagging, and counting the total number of socks of each machines too at the same time. It not only automated the system but also reduced the expenses of computers and human power. (ISO certified company).

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    High Speed AES    image

    AES encryption and Decryption Implementation on Xilinx Vertix-5 FPGA in VHDL.

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    DVB-CSA    image

    High speed DVB-Common Scrambling Algorithm (CSA) on Xilinx Vertix-5 FPGA in VHDL.

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    FM Antenna Direction & Angle Detector    image

    Finding the direction and angle of transmitter antenna with respect to three reference receiver antennas that were receiving FM signals. It includes A/D and D/A conversion and samplings and finding FFTs, IFTs, Complex number and their operations, and complex equation calculations and all that done over Xilinx Virtex-4 FPGA integrating different tools of XILINX in order to make it complete project.

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    Signal Generator & Shifter    image

    Generation of 4 sign waves over Xilinx FPGA without using any sine wave as input and capable of shifting any wave according to the user requirement. Sample of these sine waves are not hardcoded but calculated on run time. These waves next were used to change the direction of signal lobs of array antenna.

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    Face Recognition System    image

    PCA algorithm is used to implement the image comparison method using VHDL language over Xilinx Spartan 3E FPGA.

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    SHA-1    image

    High speed SHA-1 Security Algorithm implementation on Xilinx Virtex-4 FPGA in VHDL.

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    ADPCM    image

    ADPCM implementation using Xilinx System Generator integrated with Xilinx ISE on Xilinx Virtex-5.

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    Electronics Business Management System    image

    C# based efficient, power full and easy to use software for any kind of import/export business, mart and shopping outlets. Contains many powerful and unique features that give the user 95% fully automated management and control. Synched with website and database to maintain data/records and for data backup.

    ASP.net based business website allowing user and management to control things from web site. Have user accounts and login system along with online shopping system. Synched with software being used at PC side and updates database and backup automatically while maintaining different things.

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A pulsedindex technique for single-channel, low-power, dynamic signaling    image

Shahzad Muzaffar, Ayman Shabra, Jerald Yoo, and Ibrahim (Abe) M. Elfadel
Conference Papers Design, Automation and Test In Europe (DATE), Grenoble, France, pp. 1485-1490, March 2015

Abstract

The most common operation of an IoT sensor is that of short activity bursts separated by long time intervals in sleep or listen modes. During the data bursts, sensed information has to be reliably communicated in real time without draining the energy resources of the sensor node. One way to save such resources is to efficiently code the data burst, use single-channel communication, and adopt ultra-low-power communication circuit techniques. Clock-data recovery (CDR) circuits are typically significant consumers of energy on traditional single-channel communication protocols. In this paper, we present a novel single-channel protocol that does not require any CDR circuitry. The protocol is based on the novel concept of a pulsed index where data is encoded to minimize the number of ON bits, move them to the LSB end of the packet, and transmit the ON bit indices in the form of a pulse stream. The pulse count is equal to the index of the ON bit. We call this protocol Pulsed Index Communication (PIC). Beside the elimination of CDR, we show that the implementation of PIC is very area-efficient, low-power and highly tolerant of clocking differences between transmitter and receiver. We present both an FPGA and an ASIC implementation of the protocol and use them to illustrate the performance, reliability and power consumption features of PIC signaling. In particular, we show that for an ASIC implementation on 65nm technology, PIC can reduce area by more than 80% and power by more than 70% in comparison with a CDR-based serial bit transfer protocol.

Timing and Robustness Analysis of Pulsed-Index Protocols for Single-Channel, Low-Power, Dynamic Signaling    image

Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel
Conference Papers International Conference on Very Large Scale Integration (VLSI-SoC), Daejeon, Korea, pp. 225-230, October 2015

Abstract

Pulsed-Index Communication (PIC) is a novel technique for single-channel, high-data-rate, low-power dynamic signaling that does not require any clock and data recovery. It is fully adapted to the simple yet robust communication needs of IoT devices and sensors. In this paper, we present a full quantitative analysis of the timing and robustness properties of PIC protocols, including the impact of important protocol parameters such as pulse width and inter-symbol delays on average data rate and protocol robustness with respect to clock variations. The main result of this paper is a theoretical upper bound on clock variability between transmitter and receiver below which the protocol operates with zero decoding error over an ideal channel. This bound is verified experimentally using a full FPGA implementation that includes point-to-point transmission between two TI MSP430 microcontrollers, acting as two IoT sensor nodes over a single-wire connection.

Power Management of Pulsed-Index Communication Protocols    image

Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel
Conference Papers IEEE International Conference on Computer Design (ICCD), New York, USA, pp. 375-378, October 2015

Abstract

Pulsed-Index Communication (PIC) is a novel technique for single-channel, high-data-rate, low-power dynamic signaling that does not require any clock and data recovery. It is fully adapted to the simple yet robust communication needs of the body area network, IoT devices, and sensors. Prior work has focused on the power savings that this protocol can achieve as a result of the elimination of circuitry devoted to clock and data recovery. In this paper, we show that further power saving can be achieved using the duty cycle of the pulse as a power control parameter. This power control policy is applied to both a single-wire link and a wireless body-communication channel with significant power saving achieved above and beyond the clock and data recovery. These power savings are obtained without any impact on data rate. The pulse control policy is implemented using 45nm CMOS technology and verified on various communication links, involving single channels.

Automatic Protocol Parameter Detection and Adaptive Baud Rates in Single-channel, Low-power Dynamic Signaling for IoT Devices    image

Shahzad Muzaffar, Numan Saeed, and Ibrahim (Abe) M. Elfadel
Conference Papers International Conference on Very Large Scale Integration (VLSI-SoC), Tallin, Estonia, September 2016
(Accepted)

Abstract

Pulsed-Index Communication (PIC) is a novel technique for single-channel, high-data rate, low-power dynamic signaling that does not require any clock and data recovery. It is fully adapted to the simple yet robust communication needs of Internet of Things (IoT) devices and sensors. However, its error-free operation with maximum data rate requires a careful and judicious setting of PIC data packet and pulse timing parameters. In this paper, we present an algorithm for automatically detecting the PIC protocol parameters at the power-on phase and to removing the restriction on all the devices in the PIC network to follow a particular communication speed. The hardware realization of the algorithm is power-efficient and uses closed-form formulas that assign suitable protocol parameters to both ends of the transmission link based on the clock rate difference. This difference is determined by a preliminary exchange of clock pulse streams between the transmitter and the receiver. The automatic parameter setting remains operational even in the presence of variations between the clock frequencies of the IoT devices communicating via PIC. The mechanism is illustrated in the case of several IoT devices that are using different clock frequencies and are in need to synchronize their communication parameters with respect to the clock frequency of a master gateway. A power-on PIC parameter configuration process is rigorously specified, and both an FPGA and an ASIC implementations are presented. In particular, we show that for an ASIC implementation in 65nm technology, the low-power operation of PIC is maintained, consuming only 4.35 uW of power at a clock frequency of 25 MHz. This architecture is experimentally verified and tested on a point-to-point communication link between two IoT devices connected via a single PIC channel in a master-slave mode.

An Integrated, Low-Power Platform for Continuous Congestive Heart-Failure Monitoring    image

Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel
Journal Paper IEEE Transactions on Computer Aided Design (TCAD) of Integrated Circuits and Systems
(Under Review)

Abstract

This research presents a novel architecture of an ultra-low power wearable system for Congestive Heart Failure (CHF) monitoring using the continuous measurement of a patient's weight to detect changes in body mass and fluid composition. Shoe-integrated sensor arrays are used to continuously measure the weight, and an electronic digital assistant, implemented in VLSI, is used to further analyze the acquired measurements in real time. To achieve ultra low-power operation, the human body is used as a communication medium between the shoe-mounted sensors and the digital assistant. The single-channel behavior of the human body is accommodated with a novel, simple yet robust single-wire signaling technique that is called Pulsed-Index Communication (PIC). This signaling technique significantly reduces the system footprint and its overall power consumption as it entirely eliminates the need for circuitry dedicated to clock and data recovery. The proof-of-concept CHF system has been prototyped using a cutting-edge FPGA platform, namely, Virtex 7 from Xilinx. The prototype, which integrates models for footwear, body communication channel (BCC), and back-end digital electronics, has been rigorously and successfully tested. This highly modular system is being used to implement, analyze and compare various pattern recognition algorithms for the early detection of congestive heart failure.

Pulsed-Index Communication: Design, Optimization, and Implementation    image

Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel
Journal Paper IEEE Transactions on Very Large Scale Integration (VLSI) Systems
(In Preparation)

Abstract

Continuous Real-time Monitoring and early Detection of Congestive Heart-Failure Conditions: An Enhanced Low-Power Adaptive-Grid Run-Time Systematic Sampling Technique    image

Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel
Conference Papers
(In Preparation)

Abstract

A versatile hardware platform for the development and characterization of IoT sensor networks    image

Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel
Conference Papers UAE GSRC, Al-Ain, UAE, April 17-18, 2015

Abstract

We present an FPGA hardware platform for the prototyping and analysis of ultra-low power IoT sensor networks. The platform is meant to address the problem of evaluating network topology design options for IoT sensor communications using single-channel communication protocols. The network topologies include bus, star, ring, and tree topologies. This FPGA-based IoT network platform is based on three fundamental ingredients: a full HDL implementation of ultra-low power TI MSP530 microcontroller; a novel ultra-low power single-wire communication protocol that does not require any clock and data recovery, the protocol is called pulsed-index communication (PIC); embedded C implementation of the PIC transceivers within the TI MSP430 without any need for external hardware circuitry. In one of our bus network analysis, we have used the Virtex-7 FPGA environment to instantiate the TI MSP 430 a number of times equal to the number of IoT sensors and used simple sensor ID's to implement high-throughput, ultra-low power network communication between the IoT sensors using embedded C programs. Message collision is avoided using the built-in properties of PIC. The platform is flexible in that it allows the design, analysis and comparison of various networking graph topologies among the IoT sensors, including ones that contain gateways and hubs. The platform is also scalable in that the resources used for a two-sensor, point-to-point communication link is less than 1% of the Virtex-7 available hardware.

An Integrated, Low-Power Platform for Continuous Congestive Heart-Failure Monitoring    image

Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel
Conference Papers Design, Automation and Test In Europe (DATE), Dresden, Germany, March 14-18, 2016
(Project Demonstration)

Abstract

A versatile hardware platform for the development and characterization of IoT sensor networks    image

Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel
Conference Papers SRC’s TECHCON, Austin, TX, September 20-22, 2015
(Work-In-Progress Presentation)

Abstract

Design and Analysis of Pulsed-Index Protocols for Single-Channel, Low-Power, Dynamic Signaling    image

Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel
Conference Papers Design Automation Conference (DAC), San Francisco, CA, June 7-11, 2015
(Work-In-Progress Presentation)

Abstract

Pulsed-Index Communication (PIC) is a novel technique for single-channel, high-data rate, low-power dynamic signaling that does not require any clock and data recovery. It is fully adapted to the simple yet robust communication needs of IoT devices and sensors. In this paper, we present a full theoretical framework that underlies the design, analysis and optimization of PIC protocols. In particular, we show how this framework can be used to rigorously maximize the data rate for a given combination of message length, encoding policy, and tagging cost. The theoretical framework further allows the derivation of the statistical distributions of data rates for various channel models. In addition, we identify the noise sources contributing to PIC error rates and recommend simple correction schemes for reducing bit error rates.

Ultra Low-Power Method for Single Wire Communication

Patent 2015, Provisional Patent Registration no. = 53455

Abstract

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Design and Analysis of Pulsed-Index Protocols for Single-Channel, Low-Power, Dynamic Signaling

Patent 2015, (In Disclosure Preparation)

Abstract

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Automatic Weight Estimation Using Footwear Sensors

Patent 2015, (In Disclosure Preparation)

Abstract

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Currrent Teaching

  • 2015 2014

    Digital Systems Lab

    Teaching Assistant in Microsystems department at Masdar Institute. Conducting labs and supervising student projects.

Teaching History

  • 2011 -

    Workshops on Xilinx FPGA Design Tools & Flows

    Workshops on Xilinx FPGA Design Tools with VHDL/Verilog and embedded systems design flow at CEFAR, NUST-SEECS. Delivered lectures and conducted labs to provide hands-on experience to the professionals and students.

  • 2010 -

    Object Oriented Programming

    Lab instructor at NUST-SEECS. Designed, developed and conducted labs on C++ programming.

  • 2009 -

    Programming for Engineers II

    Lab instructor in EE department at FAST-NUCES. Designed, developed and conducted labs on C++ programming.

At My Lab

You can find me at my research desk located at level-2, lab-3 (right side), beside Dr. Mihai's room, Building 1-A, Masdar Institute.

If I am not on my desk, please try to reach me in my room.

At My Room

You can find me at my room (Geo. 4.02) located at 4th floor of Geo. Thermal residential block, Building 1-B, Masdar Institute.

If you are still unable to find me, please contact me through my cell number or by e-mail.