Shahzad Muzaffar

Shahzad Muzaffar

About Me

PhD Student

Short Bio

Shahzad Muzaffar is a final year PhD student at Masdar Institute (In collaboration with MIT), Khalifa University of Science and Technology, Abu-Dhabi, UAE. He received his M.Sc. degree (Microsystems Eng.) from the same institute in 2015 and the B.Sc. degree from the Electrical Engineering Department, National University of Computer and Emerging Sciences (NUCES - FAST), Lahore, Pakistan in 2008. His research work is multidisciplinary with the objectives to explore the novel and unconventional ideas and methods to solve challenging and untapped real-world problems with the help of innovations in the realm of digital circuits and systems. In appreciation of the quality of his work on M.Sc. thesis project he was awarded the Microsystems Department's Best Thesis Award as well as the Institute's Best Thesis Award.

From 2011 to 2013, he held a position of senior development engineer in ESD division at the Mentor Graphics, Lahore, Pakistan. From 2009 to 2011, he was Design Engineer (Team Lead) at the Center for Excellence in FPGA/ASIC Research (CEFAR), National University of Sciences and Technology, Islamabad, Pakistan. Throughout his educational and professional career, he was awarded several other Best Project and Best Performance awards.

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Education

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Experience

Research | Professional

Awards & Honors

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Extracurricular & Hobbies

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Awards & Extracurricular

Awards & Honors

  • Institute's Best M.Sc. Thesis Award
    @ Masdar Institute
  • Department's Best M.Sc. Thesis Award
    @ Masdar Institute
  • Outstanding Performance Award
    @ Mentor Graphics
  • Outstanding Project Award
    @ National University of Computer and Emerging Sciences
  • Winner of International Programming Competition (ACM mentored) in SOFTEC at FAST-NUCES, Lahore.
  • Multiple time winner of Speed Programming Competition in NASTEC at NUST, Islamabad.
  • Stood in top 5 teams in International Engineering Project Competition in SOFTEC at FAST-NUCES, Lahore.
  • Invited several times to judge different engineering competitions in ACM and SOFTEC events at FASTNUCES, Lahore.
  • Secured several scholarships and financial aids to support my education.

Extracurricular & Hobbies

  • Table Tennis & other indoor spots
  • Cricket
  • Reading
  • Graphic designing and animations
  • Sound and Video editing

Research

My Research, Patents, Publications

Research Interests

My objectives are to explore the novel and unconventional ideas and methods to solve challenging real-world problems and uncover untapped potentials, methods and systems, and realize these onerous methods and full systems from scratch to the final demonstrate-able shape by solving the cropped up challenges for all the required ingredients with the help of innovations in the realm of digital circuits and systems that may engage:

  • The design of new digital integrated circuit modules (VLSIs, ASICs, SoCs, etc.).
  • One or multiple existing technologies (FPGAs, DSPs, Embedded Systems, etc.).
  • Novelty in digital logic and architecture design.
  • Area-Power efficient and high-speed hardware translation of complex algorithms and systems.
  • Specialized processors and processing device architectures.
  • Reconfigurable systems: Applications, Circuits, and Systems.
  • Not only logical circuit design but also system-level prototypes, architecture, integration, interfacing, system testing/verification, and other miscellaneous practical implementation aspects.

Currently, I am focused on and working to solve challenges related to healthcare / health monitoring systems and low-end IoT devices by proposing and developing new techniques and methodologies.

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Patents & Publications

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Research & Work-In-Progress Demos, Workshops

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Research Experience

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Patents & Publications

6 Patents, 20 Publications

Patents

[1] Systems and Methods for Low-power Single-wire Communication (US Patent Filed. Application Number: 15/807,854)
[2] Apparatus And Method For Weight Measurement During Motion Using Force Waveforms (US Patent Filed. Application Number: 16/023,287)
[3] Sensor Array For Consolidated Force Measurement (US Patent Filed. Application Number: 16/023,335)
[4] Systems And Methods For Self-Synchronized Communications (US Patent Filed. Application Number: 16/023,356)
[5] Method for Secure Device-to-Device Communication using Multilayered Cyphers (US Patent Filed. Application Number: 16/047,375)
[6] Wearable Walk and Weight Monitoring System (Disclosure submitted for US patent filing)

Publications

Books & Book Chapters

[1] "Low-power, Dynamic-data-rate Protocol for IoT Communication," in The IoT Physical Layer - Design and Implementation, Springer, 2018, pp. 193-231.
[2] "Toward An Integrated, Low-power Platform for Continuous Congestive Heart-failure Monitoring," in The IoT Physical Layer - Design and Implementation, Springer, 2018, pp. 327-352.
[3] "Pulsed Decimal Encoding for IoT Single-channel, Dynamic Signaling," in VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things. Springer, 2018. (In Press)
[4] S. Muzaffar and I. M. Elfadel, Pulsed-Index Communication Family. Springer, 2019. (In Preparation)
 

Conferences & Journals

[5] S. Muzaffar A. Shabra, J. Yoo, and I. M. Elfadel, "A Pulsed-Index Technique for Single-Channel, LowPower, Dynamic Signaling," Design, Automation and Test In Europe (DATE'15), pp. 1485--1490, Grenoble, France, March 2015.
[6] S. Muzaffar and I. M. Elfadel, "Timing and Robustness Analysis of Pulsed-Index Protocols for Single-Channel IoT Communications," 23rd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2015), pp. 225--230, Daejeon, South Korea, October 2015.
[7] S. Muzaffar and I. M. Elfadel, "Power Management of Pulsed-Index Communication Protocols," 33rd IEEE International Conference on Computer Design (ICCD), pp. 375--378, New York, NY, USA, October 2015.
[8] S. Muzaffar N. Saeed, and I. M. Elfadel. "Automatic protocol configuration in single-channel low-power dynamic signaling for IoT devices," 24th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2016), pp. 1--6, Tallinn, Estonia, September 2016.
[9] S. Muzaffar and I. M. Elfadel. "A versatile hardware platform for the development and characterization of IoT sensor networks," 59th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'16), pp. 1--4, Abu Dhabi, UAE, October 2016.
[10] S. Muzaffar O. T. Waheed, Z. Aung, and I. M. Elfadel, "Single-clock-cycle, Multilayer Encryption Algorithm for Single-channel IoT Communications," IEEE Conference on Dependable and Secure Computing (DSC 2017), pp. 153--158, Taipei, Taiwan, August 2017.
[11] S. Muzaffar and I. M. Elfadel, "A Pulsed Decimal Technique for Single-channel, Dynamic Signaling for IoT Applications," 25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017), pp. 1--6, Abu Dhabi, UAE, October 2017.
[12] S. Muzaffar and A. Afshari, "Short-Term Load Forecasts Using LSTM Networks," International Conference on Applied Energy (ICAE 2018), Hung Hom, Hong Kong, August 2018.(Accepted)
[13] S. Muzaffar and I. M. Elfadel, "An Instruction Set Architecture for Low-power, Dynamic IoT Communication," 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2018), Verona, Italy, October 2018.(Accepted)
[14] S. Muzaffar and I. M. Elfadel, "A Novel CDR-Less Dynamic Signaling Technique for IoT Communication," IEEE Internet of Things Journal. (Under review).
[15] S. Muzaffar and I. M. Elfadel, "A Self-synchronizing, Low-power, and Small Form-factor Human-Body Communication Transceiver using Pulsed-Index Communication," IEEE International Symposium on Circuits & Systems (ISCAS 2019), (Submitted).
[16] S. Muzaffar and I. M. Elfadel, "A Method of Sensor Array Design Using Shoe Integrated Sandwiched Sensor Force Consolidators (SSFC) for Total Force Measurement," IEEE Engineering in Medicine and Biology Conference (EMBC 2019). (Submitted).
[17] S. Muzaffar and I. M. Elfadel, "A Domain Specific Processor Architecture for Low-power, Dynamic IoT Communication," IEEE Transactions on Very Large Scale Integration (VLSI) Systems. (Ready to Submit).
[18] S. Muzaffar and I. M. Elfadel, "Single-clock-cycle, Multilayer Encryption Algorithm for Single-channel IoT Communications," IEEE Transactions on Very Large Scale Integration (VLSI) Systems. (Ready to Submit).
[19] S. Muzaffar and I. M. Elfadel, "Self-Synchronized and Motion Sensor-Free Method for Weight Estimation During Walk and Run," Journal to be Decided. (Ready to Submit).
[20] S. Muzaffar and I. M. Elfadel, "An Embedded Walk-cycle Monitoring System using Body Area Communication and Secure Low-power Dynamic Signaling," Journal to be Decided. (In preparation).

Research Demos, Workshops

[1-2] Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel, "An Embedded Walk-cycle Monitoring System using Body Area Communication and Secure Low-power Dynamic Signaling," (Project Demonstration/Presentation)
  1. Design, Automation and Test In Europe (DATE), Dresden, Germany, March 19-23, 2018.
  2. Graduate Students Research Conference (GSRC), Sharjah, UAE, April 21, 2018.
  3. Graduate Students Research Conference (GSRC), Abu Dhabi, UAE, March 20-21, 2017.
[3-5] Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel, "An Integrated, Low-Power Platform for Continuous Congestive Heart-Failure Monitoring," (Project Demonstration)
  1. Design, Automation and Test In Europe (DATE), Dresden, Germany, March 14-18, 2016.
  2. IEEE Engineering in Medicine and Biology Society (EMBS), Sharjah, UAE, May 7, 2016.
  3. Graduate Students Research Conference (GSRC), Abu-Dhabi, UAE, April 17-18, 2015.
[6-7] Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel, "A versatile hardware platform for the development and characterization of IoT sensor networks," (Work-In-Progress Demo Presentation)
  1. SRC's TECHCON, Austin, TX, USA, September 20-22, 2015.
  2. Graduate Students Research Conference (GSRC), Al-Ain, UAE, April 27-28, 2016.
[8-9] Shahzad Muzaffar, Owais Talaat, Z. Aung, and Ibrahim (Abe) M. Elfadel, "Single-clock-cycle, Multilayer Encryption Algorithm for Single-channel IoT Communications," (Competition and Research Presentation)
  1. SRC's TECHCON, Austin, TX, USA, September 16-18, 2018.
  2. Cyber Security Awareness Week (CSAW'17), NYU, UAE, November 9-11, 2017. Third Prize Winner.
[10] Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel, "Design and Analysis of Pulsed-Index Protocols for Single-Channel, Low-Power, Dynamic Signaling," Design Automation Conference (DAC), San Francisco, CA, UASA, June 7-11, 2015. (Work-In-Progress Demo Presentation)
[11] Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel, "A Pulsed-Decimal Technique for Single-channel, Dynamic Signaling for IoT Applications," SRC's TECHCON, Austin, TX, USA, September 10-12, 2017. (Demo Presentation)
[12] Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel, "A Special-Purpose Instruction Set and Microarchitecture for Low-power, Dynamic IoT Communication," Design Automation Conference (DAC), San Francisco, CA, UASA, June 24-28, 2018. (Design/IP Presentation)
[13] Shahzad Muzaffar, and Ibrahim (Abe) M. Elfadel, "IoT Platform for Detecting Continuous Congestive Heart-Failure," UAE Society of Engineers, Dubai, UAE, April 2018. (Delivered Workshop)

Reseach Experience

5+ Years

Research Experience

Sep. 2013 - Present

Research Assistant

Institute Center for Microsystems (iMicro), ATIC-SRC Center of Excellence for Energy Efficient Electronics Systems (ACE4S), Masdar Institute, Khalifa University of Science and Technology, Abu-Dhabi, UAE
  • Task Leader: Prof. Ibrahim (Abe) M. Elfadel, MI.
  • Co-Task Leaders: Prof. Anantha P. Chandrakasan (MIT), Prof. Jerald Yoo (MI, 2013-16), and Prof. Ayman Shabra (MI, 2013-15).

I did a multidisciplinary research work on the problem of wearable Continuous Healthcare Monitoring System, from planning to architectural definition, design, implementation, and testing of final working hardware prototype demonstrator. The work proposed a new way of health monitoring and early diagnosis based on continuous weight estimation that is very challenging and has not been explored yet. During my tenure at Masdar Institute, I worked on a range of aspects of this project, briefly stated ahead. I would like to acknowledge my advisor for all the guidance, flexibility and support he offered me which enabled me to take risks and work on untapped new methods to accomplish all the tasks as a lone student researcher on this strenuous project.

Monitoring System & Methodologies

  • Developed a wearable continuous health monitoring system by continuously estimating subject's weight, hence the weight change patterns, both during the walk and when the subject is stationary. The system has several parts and some of these are as following.
    • Proposed a new method of integrating sensors in shoe insoles to enable full force collection for weight estimation.
    • Proposed methods for weight estimation during walk or run at various speeds by employing the extraction of key features from walk-cycle waveforms which have not been explored yet for weight estimation.
    • Proposed force adjustment and error correction methods for the low-cost pressure sensors that are used to build the demonstrator shoe system.
  • Algorithms to realize the proposed methods are developed and verified.
  • A full wearable demonstrator prototype using the above mentioned methods and the following communication techniques is developed to showcase the end-to-end success of the system and is verified on real-world subjects.
  • The developed system is intended to be used in various domains such as to diagnose a range of health problems on early basis (for example congestive heart failure, cancer, etc..), daily-life style monitoring to prevent health issues, to create databases on weight change patterns to help further research, to control balance in robotics as well as for sports medicines, animal healthcare/sports, prostheses, gait analysis, and etc.

New CDR-less Communication Techniques

  • Invented a family of novel CDR-less, low-power, high data rate, and dynamic single-channel communication techniques named as Pulsed-Index Communication Family (PIC Family)..
  • Proposed member techniques:.
    • Pulsed-Index Communication (PIC) in 2015
    • Pulsed-Decimal Communication (PDC) in 2017
    • Pulsed-Index Communication Plus (PICplus) in 2018
  • IP implementation of PIC member techniques in Verilog for FPGA (Virtex-7), ASIC flow (synthesized with 65nm CMOS technology), and in embedded C.
  • Did detailed optimization and analysis.
  • Power Management: Presented a detailed PHY layer power management policy based on pulse duty cycle control for the Pulsed-Index Communication protocols to improve further their ultra-low power characteristics without impacting their data or bit error rates. Implemented using 45nm CMOS technology.
  • Automatic Parameters Configuration: The power-on algorithmic process for automatically detecting the PIC protocol parameters allows the master device to configure all the slave devices connected to a single-channel PIC network prior to the start of any device-to-device communication while removing the restriction on devices to communicate at a specified baud rate. Implemented in Verilog on the Xilinx Virtex-7 FPGA platform and ASIC flow (synthesized with 65nm CMOS technology).
  • IoT Platform: IoT characterization and testing platform using a network of devices connected via PIC family protocol. Implemented on Virtex-7 using PIC and TI MSP430 Verilog IP.
  • Multilayer Encryption/Decryption: The proposed single-channel, secure communication system exploits the unique features of PIC technique to add multilayer security to the transmission with low impact on PIC performance while presenting a set of hard-to-solve challenges to an attacker. Prototyped both in FPGA and ASIC (65nm CMOS technology).
  • Special Purpose Processor and ISA: Proposed a special-purpose processor (microarchitecture) along with the tuned ISA that supports both the standard and customized pulsed-signaling protocols and enables the amalgamation of software and hardware to greatly reduce the number of instructions required to implement a given communication interface without impacting either the data rates and or the reliability of the protocols. Prototyped both in FPGA and ASIC (synthesized with 65nm CMOS technology).

Body-Channel Communication (BCC)

  • First successful two-way communication through human body channel (i.e., sending a real bit stream instead of testing using clock stream or by spectral analysis).
  • Proposed and implemented simplified low-power and small form factor BCC transceiver.
  • PIC member techniques are used for BCC that helped in reducing the hardware complexity and removing various duty cycle related issues.
  • A second BCC demonstrator is also developed using music signal transmission through human skin.

Miscellaneous

  • Continuous Real-time Monitoring and early Detection of Congestive Heart-Failure Conditions: An Enhanced Low-Power Adaptive-Grid Run-Time Systematic Sampling Technique.
  • Multiparameter Heart Failure Monitoring Algorithm-Initial Implementation using 45nm CMOS technology.
  • ALU Architecture implementation using 45nm CMOS technology.
  • Differential Digital Clock \& Data recovery (CDR) using Virtex-7 FPGA.
Oct. 2009 - Jan. 2011

Design Engineer (Team Lead)

Center for Excellence in FPGA/ASIC Research (CEFAR), National University of Sciences and Technology (NUST), Islamabad, Pakistan

Worked on several projects such as:

  • Secure dial project to securely transmit the speech over telephones using Xilinx Virtex-5 FPGA.
  • AES encryption and Decryption implementation on Xilinx Virtex-5 FPGA.
  • ADPCM implementation on Xilinx Virtex-5 FPGA.
  • High speed DVB-Common Scrambling Algorithm (CSA) implementation on Xilinx Virtex-5 FPGA.
  • High speed SHA-1 Security Algorithm implementation on Xilinx Virtex-4 FPGA.
  • Power optimization techniques at RTL level to reduce power consumption of FPGA based system designs.
Aug. 2008 - June 2015

University Research Projects Mentoring and Supervision

  • Electrical Engineering Department, National University of Computer and Emerging Sciences (NUCES-FAST), Lahore.
    • FPGA based CPPI Supported Mini-Computer. Hardware (XilAnt) on Virtex-4 FPGA and OS Wrapper (XilAntOS) using Xikernel/Mentor-Nucleus and embedded C - Outstanding Project Award.
    • Improved FALCON-A Processor Architecture over FPGA (Virtex-4).
    • FM Antenna Direction & Angle Detector using FPGA Platform (Virtex-4).
    • FPGA Based Signal Generator \& Shifter (Spartan-3E).
    • FPGA Implemented Face Recognition System (Virtex-4).
    • High Speed Big Data (0-512 bit) Multiplier over FPGA (Spartan-3).
    • Energy Management System (Virtex-4).
  • Computer Engineering Department, COMSATS Institute of Information Technology, Lahore.
    • Custom OS image editor using FPGA based embedded system (Spartan-6) - Best Project Award.

Academics

Education, Teaching

Education

Sep. 2015 - Present

Doctor of Philosophy (Ph.D.) - Microsystems Engineering

Masdar Institute (In Collaboration with MIT), Khalifa University of Science and Technology, Abu-Dhabi, UAE
  • Thesis Title: An Embedded Walk-cycle Monitoring System using Body Area Communication and Secure Low-power Dynamic Signaling.
  • Advisor: Prof. Ibrahim (Abe) M. Elfadel, MI.
  • RSC Members:
    • Prof. Neville Hogan, Head of Mechanical Engineering, MIT.
    • Prof. Mihai Sanduleanu, MI.
  • Sponsors and Collaborators: SRC, Mubadala, MIT.
  • Knowledge Involved but Not Limited to: IC / VLSI Design, FPGA Based Design, Algorithm Development, System Architecture & Integration, PCB Design, Communication & Synchronization, Power Management, Testing and Analysis.

Know more:    List of Courses , About Thesis

Sep. 2013 - Aug. 2015

Master of Science (M.Sc.) - Microsystems Engineering

Masdar Institute of Science and Technology (In Collaboration with MIT), Abu-Dhabi, UAE
  • Thesis Title: An Integrated, Low-Power Platform for Continuous Congestive Heart-Failure (CHF) Monitoring using Body-Channel Communication.
  • Advisor: Prof. Ibrahim (Abe) M. Elfadel, Head of Institute Center for Microsystems (iMicro), MI.
  • Co-Advisors: Prof. Jerald Yoo and Prof. Ayman Shabra.
  • Accolade: Institute's Best Thesis Award and Microsystems Department's Best Thesis Award.
  • Sponsors and Collaborators: SRC, Mubadala, MIT.
  • Knowledge Involved but Not Limited to: IC / VLSI Design, FPGA Based Design, Algorithm Development, System Architecture & Integration, PCB Design, Communication & Synchronization, Power Management, Testing and Analysis.

Know more: List of Courses ,    About Thesis

Aug. 2004 - June 2008

Bachelor Of Science (B.Sc.) - Electrical Engineering

National University of Computer and Emerging Sciences (NUCES-FAST), Lahore, Pakistan
  • Project Title: Learning Robo - An external and general learning systems for machines.
  • Advisor: Prof. Imtiaz Tariq.
  • Accolade: Outstanding Project Award in the EE department sponsored in-house competition, and graduated among the top 5% of my class.

Know more:    List of Courses

Teaching Experience

2014-15 Lab instructor for ``Digital Systems Lab'' in Microsystems department at Masdar Institute. Prepared material, conducted labs, and supervised student projects.
2011 Workshops on Xilinx FPGA Design Tools with VHDL/Verilog and embedded systems design flow at CEFAR, NUST-SEECS. Delivered lectures and conducted labs to provide hands-on experience to the professionals and students.
2010 Lab instructor for ``Programming for Engineers II'' at NUST-SEECS. Designed, developed and conducted labs on C++ programming.
2009 Lab instructor for ``Object Oriented Programming'' at NUCES-FAST. Designed, developed and conducted labs on C++ programming.
- I delivered many tutorial lectures at various institutes including, NUCES-FAST, NUST, and Masdar Institute.

MSc Thesis

Best Thesis Award

An Integrated, Low-Power Platform for Continuous Congestive Heart-Failure (CHF) Monitoring using Body-Channel Communication


  • Advisor: Prof. Ibrahim (Abe) M. Elfadel, Head of Institute Center for Microsystems (iMicro), MI.
  • Co-Advisors: Prof. Jerald Yoo and Prof. Ayman Shabra.
  • Accolade: Institute's Best Thesis Award and Microsystems Department's Best Thesis Award.
  • Sponsors and Collaborators: SRC, Mubadala, MIT.
  • Knowledge Involved but Not Limited to: IC / VLSI Design, FPGA Based Design, Algorithm Development, System Architecture & Integration, PCB Design, Communication & Synchronization, Power Management, Testing and Analysis.

Abstract:

This research presents a novel ultra-low power wearable system for Congestive Heart Failure (CHF) monitoring using the continuous measurement of a patient's weight to detect changes in body mass and fluid composition. Shoe-integrated sensor arrays are used to continuously measure the weight, and an electronic digital assistant, implemented in VLSI, is used to further analyze the acquired measurements in real time. To achieve ultra low-power operation, the human body is used as a communication medium between the shoe-mounted sensors and the digital assistant. The single-channel behavior of the human body is accommodated with a novel, simple yet robust single-wire signaling technique that we have called Pulsed-Index Communication (MI provisional patent pending). This signaling technique significantly reduces the system footprint and its overall power consumption as it entirely eliminates the need for circuitry dedicated to clock and data recovery. The CHF system has been fully prototyped using a cutting-edge FPGA platform, namely, Virtex 7 from Xilinx. The prototype, which integrates models for footwear, body area network (BAN), and back-end digital electronics, has been rigorously and successfully tested. This highly modular system is being used to implement, analyze and compare various pattern recognition algorithms for the early detection of congestive heart failure. The research described in this thesis has been conducted under the Abu Dhabi - SRC Center of Excellence on Energy-Efficient Electronic Systems (ACE4S).

System Diagram:

image

PhD Thesis

Thesis Information

An Embedded Walk-cycle Monitoring System using Body Area Communication and Secure Low-power Dynamic Signaling.


  • Advisor: Prof. Ibrahim (Abe) M. Elfadel, MI.
  • RSC Members:
    • Prof. Neville Hogan, Head of Mechanical Engineering, MIT.
    • Prof. Mihai Sanduleanu, MI.
  • Sponsors and Collaborators: SRC, Mubadala, MIT.

Abstract:

Thesis is in progress and the information will be updated during near future months.

PhD Courses

  • Environmental Sampling & Data Analysis
  • Numerical Simulation of Circuits & Systems
  • Information Security
  • Computer Architecture
  • Design & Fabrication of MEMS
  • Teaching at University Level
  • Time Series Analysis, Modeling & Prediction
  • High Performance Computing

MSc Courses

  • Analysis and Design of Digital Integrated Circuits
  • Analysis and Design of Analog Integrated Circuits
  • Digital Systems Laboratory
  • High-Speed Communication Circuits
  • Integrated Microelectronic Devices
  • Micro/Nano Processing Technology
  • Advanced Signal Processing
  • Sustainable Energy
  • Academic Writing for Research

BSc Major Courses

  • Electric Circuit Analysis
  • Electronics
  • Digital Logic Design
  • Computer Architecture
  • Microprocessor Interfacing & Programming
  • Operating System
  • Electromagnetic Theory
  • Signals & Systems
  • Digital Signal Processing
  • Digital Image processing
  • Digital Communication
  • C++ programming
  • Object Oriented Programming
  • Data Structures
  • Calculus
  • Multi Variable Calculus & Complex Analysis
  • Linear Algebra & Differential Equations
  • Feedback Control System
  • Telecommunication Systems
  • Wireless & Mobile Communication
  • Satellite Communication
  • Wave Propagation & Antenna Theory
  • Final Year Project

Downloads

Download My CV

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Professional

Professional, Administrative

Professional Experience

Feb. 2011 - Aug. 2013

Senior Development Engineer

Mentor Graphics, Lahore, Pakistan
  • Primary work was related to Digital and Embedded Systems:
    • Employed a variety of devices and development boards from vendors such as Xilinx, Texas Instruments, Freescale, Logic PD, Beagle, and ARM.
    • And, used different design tools and techniques such as Verilog/VHDL, embedded programming, board support packages, RTOS (Xilkernel and Mentor Nucleus) and, third-party IPs integration.
  • Outstanding Performance Award.
Sep. 2008 - Sep. 2009

Embedded System Engineer

Powersoft19, Lahore, Pakistan
  • Involved in an outsourced project of USA based Company, ISC, to develop devices to detect various types of harmful gasses for the workers during their work in the mines.
  • Involved in another outsourced project, ECLO-II from Germany, to automate the high speed trains in EUROPE.

Freelance Work

  • Factory machines' tracking system for an ISO certified socks knitting company (used microcontrollers as processing devices).
  • Wholesale business management system software.
  • Website developments, graphic designing, and animations.

Administrative Experience

2014-17 Managed and organized the event of Annual International Day several times at Masdar institute, thereby representing Pakistan community.
2014-17 New students mentoring and orientation arrangements under Students Affairs Office at Masdar Institute.
2013-14 Founder and President of most active students' club "mXtreme" for fun activities at large scale (i.e. sports, arts, creativity etc.) at Masdar Institute.
2008 In charge competitions of ACM, NUCES-FAST Lahore.
2008 Founder and President of ACADEMIC GUIDANCE and HELP (AGH), NUCES-FAST Lahore.

Contact & Meet Me

Get in Touch

Get in Touch

Masdar Institute, Masdar City, Abu-Dhabi, UAE
shahzad.muzaffar.fastian@gmail.com
shahzad.muzaffar@ku.ac.ae
+971 56 3300536
shahzad_muzaffar (skype)

At My Lab

You can find me at my research desk located at level-2, lab-3 (right side), beside Dr. Mihai's room, Building 1-A, Masdar Institute.

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